The Verilog HDL is a hardware description language, used for the design of ASICs and FPGAs. Verilog has a syntax reminiscent of C, which helps explain its rapid take up among engineers who had already learnt to use that language. It is case-sensitive.
It differs from C primarily in how the language represents literals and the ability to deal with time. The language (as do most hardware description languages have the ability to simulate parallel execution of multiple threads.
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History
Beginning
Verilog was first developed at Gateway Design Automation around 1984 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now had full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.
Standard Opened
With the increasing success of VHDL, Cadence moved down the Open Standards route. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog 2001
An example counter circuit follows:
//enable CEP is a clock enable only
//enable CET is a clock enable and enables the TC output
//a counter using the Verilog language
input rst; // These inputs/outputs represent connections to
input clk; // the module.
input cet;
input cep;
output [size-1:0] count;
output tc;
reg [size-1:0] count; // The reg declares storage-in hardware flip-flops
wire tc; // Wires are connections
// The always statement below is a parallel execution statement that
// executes any time the signals rst or clk transition from low to high
always @ (posedge rst or posedge clk)
begin
if (rst) // This simulates a reset of the counter
count <= 5'b0;
else if (cet && cep) // This simulates the enables both being true
begin
if (count == length-1)
begin
count <= 5'b0;
end
else
count <= count + 5'b1; // 5'b1 is 5 bits wide and
end // equal to the value 1.
end
assign tc = (cet && (count == length-1));
The other choice for assignment is an "=" operator and this is known as a blocking assignment. When the "=" operator is used, things occur in the sequence they occur much like a procedural language.
reg a,b,c,d;
always @(a or b or c)
The always clause above illustrates the other type of method of use, i.e. the always clause executes any time any of the entities in the list change, i.e. the a,b, or c change.
The resulting values of a,b,c and d above would be 0 since first "a = 0" executes, followed by "b = a", etc.Superlog/System Verilog
The advent of High Level Verification languages such as OpenVera, and Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera have been donated to Accellera. It has been transformed and updated to SystemVerilog which will likely become the next IEEE standard.Example
module Div20x (rst, clk, cet, cep, count,tc);
//TITLE 'Divide-by-20 Counter with enables'
The "<=" operator in verilog is another aspect of it's being a hardware description language as oppossed to a normal procedural language. This is known as a "non-blocking" statement. When the simulation runs, all of the signals with a "<=" operator are evaluated in parallel. This is very similar to the behavior of a real Flip/Flop. parameter size = 5;
parameter length = 20;
endmodule
Example:
begin
a = 0;
b = a;
c = b;
d = c;
end
